Modeling SiO2 Ion Impurities Aging in Insulated Gate Power Devices Under Temperature and Voltage Stress

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Antonio E. Ginart Irfan N. Ali José R. Celaya Patrick W. Kalgren Scott D. Poll Michael J. Roemer

Abstract

This paper presents a formal computational methodology to explain how the oxide in semiconductors degrades over time and the dependence of oxide degradation on voltage and temperature stresses. The effects of aging are modeled and quantified by modification of the gate-source capacitance value. The model output is validated using experimental results of a thermally aged power semiconductor device.

How to Cite

E. Ginart, A., N. Ali, I., R. Celaya, J., W. Kalgren, P., D. Poll, S., & J. Roemer, M. (2010). Modeling SiO2 Ion Impurities Aging in Insulated Gate Power Devices Under Temperature and Voltage Stress. Annual Conference of the PHM Society, 2(1). https://doi.org/10.36001/phmconf.2010.v2i1.1729
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Keywords

PHM

References
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Section
Poster Presentations

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