A Yield-Reliability Relation Modeling Approach based on Random Effects Degradation Models
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Published
Jul 14, 2017
Tao Yuan
Xiaoyan Zhu
Yue Kuo
Abstract
This paper presents a unified modeling framework for yield and reliability in micro-/nano-electronics manufacturing via spatiotemporal modeling of defects. The spatial modeling and temporal modeling of defects refer to modeling of the spatial distribution of defects in manufacturing processes and modeling of the growth of defects with time when devices are subject to stresses, respectively. The defect growth process is characterized by the random-effect degradation modeling method. The presented modeling framework will allow us to use abundantly available process control data to predict the device reliability.
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References
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Hansen, C. K., & Thyregod, P. (1996). Modeling and estimation of wafer yields and defect densities from microelectronics test structure data. Quality and Reliability Engineering International, vol. 12, pp. 9-18.
Huston, H. H., & Clarke, C. P. (1992). Reliability defect detection and screening during processing – theory and implementation. Proceedings of the International Reliability Physics Symposium, March 31-April 2. doi: 10.1109/RELPHY.1992.187656
Hwang, J. Y. (2004). Spatial stochastic processes for yield and reliability management with applications to nano electronics. Doctoral dissertation. Texas A&M University, College Station. http://oaktrust.library.tamu.edu/bitstream/handle/1969.1/1500/etd-tamu-2004C-INEN-Hwang.pdf
Hwang, J. Y., Kuo, W., & Ha, C. (2011). Modeling of integrated circuit yield using a spatial nonhomogeneous Poisson process. IEEE Transactions on Semiconductor Manufacturing, vol. 24, pp. 377-384. doi: 10.1109/TSM.2011.2143733
Kim, K. K., Kuo, W., & Luo, W. (2004). A relation model of gate oxide yield and reliability. Microelectronics Reliability, vol. 44, pp. 425-434. doi: 10.1016/j.microrel.2003.09.009
Kim, T., & Kuo, W. (1999). Modeling manufacturing yield and reliability. IEEE Transactions on Semiconductor Manufacturing, vol. 12, pp. 485-492.
doi: 10.1109/66.806126
Kuo, W. (2006). Challenges related to reliability in nano electronics. IEEE Transactions on Reliability, vol. 55, pp. 569-570. doi:10.1109/TR.2006.884585
Kuo, W., Chien, W.-T. K., & Kim, T. (1998). Reliability, yield, and stress burn-in. Boston, MA: Kluwer Academic Publishers.
Kuper, F., van der Pol, J., Ooms, E., Johnson, T., Wijburg, R., Koster, W., & Johnston, D. (1996). Relation between yield and reliability of integrated circuits: experimental results and application to continuous early failure rate deduction programs. Proceedings of the IEEE International Reliability Physics Symposium, April 30-May 2. doi: 10.1109/RELPHY.1996.492055
Meeker, W. Q., & Escobar, L. A. (1998). Statistical methods for reliability data. New York, NY: John Wiley & Sons, Inc.
Moazzami, R. M., & Hu, C. (1990). Projecting gate oxide reliability and optimizing reliability screens. IEEE Transactions on Electron Devices, vol. 37, pp. 1643-1650. doi: 10.1109/16.55751
Xuan, X., Singh, A. D., & Chatterjee, A. (2006). Lifetime prediction and design-for-reliability of IC interconnections with electromigration induced
degradation in the presence of manufacturing defects. Journal of Electronics Testing: Theory and Applications, vol. 22, pp. 471-482. doi: 10.1007/s10836-006-9498-2
Yuan, T., Ramadan, S. Z., & Bae, S. J. (2011). Yield prediction for integrated circuits manufacturing through hierarchical Bayesian modeling of spatial defects. IEEE Transactions on Reliability, vol. 60, pp. 729-741. doi: 10.1109/TR.2011.2161698
Hansen, C. K., & Thyregod, P. (1996). Modeling and estimation of wafer yields and defect densities from microelectronics test structure data. Quality and Reliability Engineering International, vol. 12, pp. 9-18.
Huston, H. H., & Clarke, C. P. (1992). Reliability defect detection and screening during processing – theory and implementation. Proceedings of the International Reliability Physics Symposium, March 31-April 2. doi: 10.1109/RELPHY.1992.187656
Hwang, J. Y. (2004). Spatial stochastic processes for yield and reliability management with applications to nano electronics. Doctoral dissertation. Texas A&M University, College Station. http://oaktrust.library.tamu.edu/bitstream/handle/1969.1/1500/etd-tamu-2004C-INEN-Hwang.pdf
Hwang, J. Y., Kuo, W., & Ha, C. (2011). Modeling of integrated circuit yield using a spatial nonhomogeneous Poisson process. IEEE Transactions on Semiconductor Manufacturing, vol. 24, pp. 377-384. doi: 10.1109/TSM.2011.2143733
Kim, K. K., Kuo, W., & Luo, W. (2004). A relation model of gate oxide yield and reliability. Microelectronics Reliability, vol. 44, pp. 425-434. doi: 10.1016/j.microrel.2003.09.009
Kim, T., & Kuo, W. (1999). Modeling manufacturing yield and reliability. IEEE Transactions on Semiconductor Manufacturing, vol. 12, pp. 485-492.
doi: 10.1109/66.806126
Kuo, W. (2006). Challenges related to reliability in nano electronics. IEEE Transactions on Reliability, vol. 55, pp. 569-570. doi:10.1109/TR.2006.884585
Kuo, W., Chien, W.-T. K., & Kim, T. (1998). Reliability, yield, and stress burn-in. Boston, MA: Kluwer Academic Publishers.
Kuper, F., van der Pol, J., Ooms, E., Johnson, T., Wijburg, R., Koster, W., & Johnston, D. (1996). Relation between yield and reliability of integrated circuits: experimental results and application to continuous early failure rate deduction programs. Proceedings of the IEEE International Reliability Physics Symposium, April 30-May 2. doi: 10.1109/RELPHY.1996.492055
Meeker, W. Q., & Escobar, L. A. (1998). Statistical methods for reliability data. New York, NY: John Wiley & Sons, Inc.
Moazzami, R. M., & Hu, C. (1990). Projecting gate oxide reliability and optimizing reliability screens. IEEE Transactions on Electron Devices, vol. 37, pp. 1643-1650. doi: 10.1109/16.55751
Xuan, X., Singh, A. D., & Chatterjee, A. (2006). Lifetime prediction and design-for-reliability of IC interconnections with electromigration induced
degradation in the presence of manufacturing defects. Journal of Electronics Testing: Theory and Applications, vol. 22, pp. 471-482. doi: 10.1007/s10836-006-9498-2
Yuan, T., Ramadan, S. Z., & Bae, S. J. (2011). Yield prediction for integrated circuits manufacturing through hierarchical Bayesian modeling of spatial defects. IEEE Transactions on Reliability, vol. 60, pp. 729-741. doi: 10.1109/TR.2011.2161698
Section
Special Session Papers